jpayne@69: /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ jpayne@69: /* jpayne@69: * Copyright (c) by Jaroslav Kysela , jpayne@69: * Creative Labs, Inc. jpayne@69: * Definitions for EMU10K1 (SB Live!) chips jpayne@69: * jpayne@69: * jpayne@69: * This program is free software; you can redistribute it and/or modify jpayne@69: * it under the terms of the GNU General Public License as published by jpayne@69: * the Free Software Foundation; either version 2 of the License, or jpayne@69: * (at your option) any later version. jpayne@69: * jpayne@69: * This program is distributed in the hope that it will be useful, jpayne@69: * but WITHOUT ANY WARRANTY; without even the implied warranty of jpayne@69: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the jpayne@69: * GNU General Public License for more details. jpayne@69: * jpayne@69: * You should have received a copy of the GNU General Public License jpayne@69: * along with this program; if not, write to the Free Software jpayne@69: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA jpayne@69: * jpayne@69: */ jpayne@69: #ifndef __SOUND_EMU10K1_H jpayne@69: #define __SOUND_EMU10K1_H jpayne@69: jpayne@69: #ifdef __linux__ jpayne@69: #include jpayne@69: #endif jpayne@69: jpayne@69: /* jpayne@69: * ---- FX8010 ---- jpayne@69: */ jpayne@69: jpayne@69: #define EMU10K1_CARD_CREATIVE 0x00000000 jpayne@69: #define EMU10K1_CARD_EMUAPS 0x00000001 jpayne@69: jpayne@69: #define EMU10K1_FX8010_PCM_COUNT 8 jpayne@69: jpayne@69: /* jpayne@69: * Following definition is copied from linux/types.h to support compiling jpayne@69: * this header file in userspace since they are not generally available for jpayne@69: * uapi headers. jpayne@69: */ jpayne@69: #define __EMU10K1_DECLARE_BITMAP(name,bits) \ jpayne@69: unsigned long name[(bits) / (sizeof(unsigned long) * 8)] jpayne@69: jpayne@69: /* instruction set */ jpayne@69: #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ jpayne@69: #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ jpayne@69: #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ jpayne@69: #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ jpayne@69: #define iMACINT0 0x04 /* R = A + X * Y ; saturation */ jpayne@69: #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ jpayne@69: #define iACC3 0x06 /* R = A + X + Y ; saturation */ jpayne@69: #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ jpayne@69: #define iANDXOR 0x08 /* R = (A & X) ^ Y */ jpayne@69: #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ jpayne@69: #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ jpayne@69: #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ jpayne@69: #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ jpayne@69: #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ jpayne@69: #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ jpayne@69: #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ jpayne@69: jpayne@69: /* GPRs */ jpayne@69: #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ jpayne@69: #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ jpayne@69: #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ jpayne@69: #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ jpayne@69: /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ jpayne@69: jpayne@69: #define C_00000000 0x40 jpayne@69: #define C_00000001 0x41 jpayne@69: #define C_00000002 0x42 jpayne@69: #define C_00000003 0x43 jpayne@69: #define C_00000004 0x44 jpayne@69: #define C_00000008 0x45 jpayne@69: #define C_00000010 0x46 jpayne@69: #define C_00000020 0x47 jpayne@69: #define C_00000100 0x48 jpayne@69: #define C_00010000 0x49 jpayne@69: #define C_00080000 0x4a jpayne@69: #define C_10000000 0x4b jpayne@69: #define C_20000000 0x4c jpayne@69: #define C_40000000 0x4d jpayne@69: #define C_80000000 0x4e jpayne@69: #define C_7fffffff 0x4f jpayne@69: #define C_ffffffff 0x50 jpayne@69: #define C_fffffffe 0x51 jpayne@69: #define C_c0000000 0x52 jpayne@69: #define C_4f1bbcdc 0x53 jpayne@69: #define C_5a7ef9db 0x54 jpayne@69: #define C_00100000 0x55 /* ?? */ jpayne@69: #define GPR_ACCU 0x56 /* ACCUM, accumulator */ jpayne@69: #define GPR_COND 0x57 /* CCR, condition register */ jpayne@69: #define GPR_NOISE0 0x58 /* noise source */ jpayne@69: #define GPR_NOISE1 0x59 /* noise source */ jpayne@69: #define GPR_IRQ 0x5a /* IRQ register */ jpayne@69: #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ jpayne@69: #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ jpayne@69: #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ jpayne@69: #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ jpayne@69: #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ jpayne@69: #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ jpayne@69: jpayne@69: #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ jpayne@69: #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ jpayne@69: #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ jpayne@69: #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ jpayne@69: #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ jpayne@69: #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ jpayne@69: jpayne@69: #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ jpayne@69: #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ jpayne@69: #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ jpayne@69: #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ jpayne@69: #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ jpayne@69: #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ jpayne@69: #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ jpayne@69: #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */ jpayne@69: #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */ jpayne@69: #define A_GPR(x) (A_FXGPREGBASE + (x)) jpayne@69: jpayne@69: /* cc_reg constants */ jpayne@69: #define CC_REG_NORMALIZED C_00000001 jpayne@69: #define CC_REG_BORROW C_00000002 jpayne@69: #define CC_REG_MINUS C_00000004 jpayne@69: #define CC_REG_ZERO C_00000008 jpayne@69: #define CC_REG_SATURATE C_00000010 jpayne@69: #define CC_REG_NONZERO C_00000100 jpayne@69: jpayne@69: /* FX buses */ jpayne@69: #define FXBUS_PCM_LEFT 0x00 jpayne@69: #define FXBUS_PCM_RIGHT 0x01 jpayne@69: #define FXBUS_PCM_LEFT_REAR 0x02 jpayne@69: #define FXBUS_PCM_RIGHT_REAR 0x03 jpayne@69: #define FXBUS_MIDI_LEFT 0x04 jpayne@69: #define FXBUS_MIDI_RIGHT 0x05 jpayne@69: #define FXBUS_PCM_CENTER 0x06 jpayne@69: #define FXBUS_PCM_LFE 0x07 jpayne@69: #define FXBUS_PCM_LEFT_FRONT 0x08 jpayne@69: #define FXBUS_PCM_RIGHT_FRONT 0x09 jpayne@69: #define FXBUS_MIDI_REVERB 0x0c jpayne@69: #define FXBUS_MIDI_CHORUS 0x0d jpayne@69: #define FXBUS_PCM_LEFT_SIDE 0x0e jpayne@69: #define FXBUS_PCM_RIGHT_SIDE 0x0f jpayne@69: #define FXBUS_PT_LEFT 0x14 jpayne@69: #define FXBUS_PT_RIGHT 0x15 jpayne@69: jpayne@69: /* Inputs */ jpayne@69: #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ jpayne@69: #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ jpayne@69: #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ jpayne@69: #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ jpayne@69: #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ jpayne@69: #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ jpayne@69: #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ jpayne@69: #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ jpayne@69: #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ jpayne@69: #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ jpayne@69: #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ jpayne@69: #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ jpayne@69: #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ jpayne@69: #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ jpayne@69: jpayne@69: /* Outputs */ jpayne@69: #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ jpayne@69: #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ jpayne@69: #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ jpayne@69: #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ jpayne@69: #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ jpayne@69: #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ jpayne@69: #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ jpayne@69: #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ jpayne@69: #define EXTOUT_REAR_L 0x08 /* Rear channel - left */ jpayne@69: #define EXTOUT_REAR_R 0x09 /* Rear channel - right */ jpayne@69: #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ jpayne@69: #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ jpayne@69: #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ jpayne@69: #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ jpayne@69: #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ jpayne@69: #define EXTOUT_ACENTER 0x11 /* Analog Center */ jpayne@69: #define EXTOUT_ALFE 0x12 /* Analog LFE */ jpayne@69: jpayne@69: /* Audigy Inputs */ jpayne@69: #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ jpayne@69: #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ jpayne@69: #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ jpayne@69: #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ jpayne@69: #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ jpayne@69: #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ jpayne@69: #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ jpayne@69: #define A_EXTIN_LINE2_R 0x09 /* right */ jpayne@69: #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ jpayne@69: #define A_EXTIN_ADC_R 0x0b /* right */ jpayne@69: #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ jpayne@69: #define A_EXTIN_AUX2_R 0x0d /* - right */ jpayne@69: jpayne@69: /* Audigiy Outputs */ jpayne@69: #define A_EXTOUT_FRONT_L 0x00 /* digital front left */ jpayne@69: #define A_EXTOUT_FRONT_R 0x01 /* right */ jpayne@69: #define A_EXTOUT_CENTER 0x02 /* digital front center */ jpayne@69: #define A_EXTOUT_LFE 0x03 /* digital front lfe */ jpayne@69: #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ jpayne@69: #define A_EXTOUT_HEADPHONE_R 0x05 /* right */ jpayne@69: #define A_EXTOUT_REAR_L 0x06 /* digital rear left */ jpayne@69: #define A_EXTOUT_REAR_R 0x07 /* right */ jpayne@69: #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ jpayne@69: #define A_EXTOUT_AFRONT_R 0x09 /* right */ jpayne@69: #define A_EXTOUT_ACENTER 0x0a /* analog center */ jpayne@69: #define A_EXTOUT_ALFE 0x0b /* analog LFE */ jpayne@69: #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ jpayne@69: #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ jpayne@69: #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ jpayne@69: #define A_EXTOUT_AREAR_R 0x0f /* right */ jpayne@69: #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ jpayne@69: #define A_EXTOUT_AC97_R 0x11 /* right */ jpayne@69: #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ jpayne@69: #define A_EXTOUT_ADC_CAP_R 0x17 /* right */ jpayne@69: #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ jpayne@69: jpayne@69: /* Audigy constants */ jpayne@69: #define A_C_00000000 0xc0 jpayne@69: #define A_C_00000001 0xc1 jpayne@69: #define A_C_00000002 0xc2 jpayne@69: #define A_C_00000003 0xc3 jpayne@69: #define A_C_00000004 0xc4 jpayne@69: #define A_C_00000008 0xc5 jpayne@69: #define A_C_00000010 0xc6 jpayne@69: #define A_C_00000020 0xc7 jpayne@69: #define A_C_00000100 0xc8 jpayne@69: #define A_C_00010000 0xc9 jpayne@69: #define A_C_00000800 0xca jpayne@69: #define A_C_10000000 0xcb jpayne@69: #define A_C_20000000 0xcc jpayne@69: #define A_C_40000000 0xcd jpayne@69: #define A_C_80000000 0xce jpayne@69: #define A_C_7fffffff 0xcf jpayne@69: #define A_C_ffffffff 0xd0 jpayne@69: #define A_C_fffffffe 0xd1 jpayne@69: #define A_C_c0000000 0xd2 jpayne@69: #define A_C_4f1bbcdc 0xd3 jpayne@69: #define A_C_5a7ef9db 0xd4 jpayne@69: #define A_C_00100000 0xd5 jpayne@69: #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ jpayne@69: #define A_GPR_COND 0xd7 /* CCR, condition register */ jpayne@69: #define A_GPR_NOISE0 0xd8 /* noise source */ jpayne@69: #define A_GPR_NOISE1 0xd9 /* noise source */ jpayne@69: #define A_GPR_IRQ 0xda /* IRQ register */ jpayne@69: #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ jpayne@69: #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ jpayne@69: jpayne@69: /* definitions for debug register */ jpayne@69: #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ jpayne@69: #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ jpayne@69: #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ jpayne@69: #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ jpayne@69: #define EMU10K1_DBG_STEP 0x00004000 /* start single step */ jpayne@69: #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ jpayne@69: #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ jpayne@69: jpayne@69: /* tank memory address line */ jpayne@69: #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ jpayne@69: #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ jpayne@69: #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ jpayne@69: #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ jpayne@69: #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ jpayne@69: jpayne@69: struct snd_emu10k1_fx8010_info { jpayne@69: unsigned int internal_tram_size; /* in samples */ jpayne@69: unsigned int external_tram_size; /* in samples */ jpayne@69: char fxbus_names[16][32]; /* names of FXBUSes */ jpayne@69: char extin_names[16][32]; /* names of external inputs */ jpayne@69: char extout_names[32][32]; /* names of external outputs */ jpayne@69: unsigned int gpr_controls; /* count of GPR controls */ jpayne@69: }; jpayne@69: jpayne@69: #define EMU10K1_GPR_TRANSLATION_NONE 0 jpayne@69: #define EMU10K1_GPR_TRANSLATION_TABLE100 1 jpayne@69: #define EMU10K1_GPR_TRANSLATION_BASS 2 jpayne@69: #define EMU10K1_GPR_TRANSLATION_TREBLE 3 jpayne@69: #define EMU10K1_GPR_TRANSLATION_ONOFF 4 jpayne@69: jpayne@69: enum emu10k1_ctl_elem_iface { jpayne@69: EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */ jpayne@69: EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */ jpayne@69: }; jpayne@69: jpayne@69: struct emu10k1_ctl_elem_id { jpayne@69: unsigned int pad; /* don't use */ jpayne@69: int iface; /* interface identifier */ jpayne@69: unsigned int device; /* device/client number */ jpayne@69: unsigned int subdevice; /* subdevice (substream) number */ jpayne@69: unsigned char name[44]; /* ASCII name of item */ jpayne@69: unsigned int index; /* index of item */ jpayne@69: }; jpayne@69: jpayne@69: struct snd_emu10k1_fx8010_control_gpr { jpayne@69: struct emu10k1_ctl_elem_id id; /* full control ID definition */ jpayne@69: unsigned int vcount; /* visible count */ jpayne@69: unsigned int count; /* count of GPR (1..16) */ jpayne@69: unsigned short gpr[32]; /* GPR number(s) */ jpayne@69: unsigned int value[32]; /* initial values */ jpayne@69: unsigned int min; /* minimum range */ jpayne@69: unsigned int max; /* maximum range */ jpayne@69: unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ jpayne@69: const unsigned int *tlv; jpayne@69: }; jpayne@69: jpayne@69: /* old ABI without TLV support */ jpayne@69: struct snd_emu10k1_fx8010_control_old_gpr { jpayne@69: struct emu10k1_ctl_elem_id id; jpayne@69: unsigned int vcount; jpayne@69: unsigned int count; jpayne@69: unsigned short gpr[32]; jpayne@69: unsigned int value[32]; jpayne@69: unsigned int min; jpayne@69: unsigned int max; jpayne@69: unsigned int translation; jpayne@69: }; jpayne@69: jpayne@69: struct snd_emu10k1_fx8010_code { jpayne@69: char name[128]; jpayne@69: jpayne@69: __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ jpayne@69: __u32 *gpr_map; /* initializers */ jpayne@69: jpayne@69: unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ jpayne@69: struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */ jpayne@69: jpayne@69: unsigned int gpr_del_control_count; /* count of GPR controls to remove */ jpayne@69: struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */ jpayne@69: jpayne@69: unsigned int gpr_list_control_count; /* count of GPR controls to list */ jpayne@69: unsigned int gpr_list_control_total; /* total count of GPR controls */ jpayne@69: struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */ jpayne@69: jpayne@69: __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ jpayne@69: __u32 *tram_data_map; /* data initializers */ jpayne@69: __u32 *tram_addr_map; /* map initializers */ jpayne@69: jpayne@69: __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ jpayne@69: __u32 *code; /* one instruction - 64 bits */ jpayne@69: }; jpayne@69: jpayne@69: struct snd_emu10k1_fx8010_tram { jpayne@69: unsigned int address; /* 31.bit == 1 -> external TRAM */ jpayne@69: unsigned int size; /* size in samples (4 bytes) */ jpayne@69: unsigned int *samples; /* pointer to samples (20-bit) */ jpayne@69: /* NULL->clear memory */ jpayne@69: }; jpayne@69: jpayne@69: struct snd_emu10k1_fx8010_pcm_rec { jpayne@69: unsigned int substream; /* substream number */ jpayne@69: unsigned int res1; /* reserved */ jpayne@69: unsigned int channels; /* 16-bit channels count, zero = remove this substream */ jpayne@69: unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ jpayne@69: unsigned int buffer_size; /* count of buffered samples */ jpayne@69: unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ jpayne@69: unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ jpayne@69: unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ jpayne@69: unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ jpayne@69: unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ jpayne@69: unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ jpayne@69: unsigned char pad; /* reserved */ jpayne@69: unsigned char etram[32]; /* external TRAM address & data (one per channel) */ jpayne@69: unsigned int res2; /* reserved */ jpayne@69: }; jpayne@69: jpayne@69: #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) jpayne@69: jpayne@69: #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) jpayne@69: #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) jpayne@69: #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) jpayne@69: #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) jpayne@69: #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) jpayne@69: #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) jpayne@69: #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) jpayne@69: #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) jpayne@69: #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) jpayne@69: #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) jpayne@69: #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) jpayne@69: #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) jpayne@69: #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) jpayne@69: #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) jpayne@69: jpayne@69: #endif /* __SOUND_EMU10K1_H */