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jpayne@69
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1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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jpayne@69
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2 /*
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jpayne@69
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3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
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4 * Creative Labs, Inc.
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jpayne@69
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5 * Definitions for EMU10K1 (SB Live!) chips
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jpayne@69
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6 *
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jpayne@69
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7 *
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jpayne@69
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8 * This program is free software; you can redistribute it and/or modify
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jpayne@69
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9 * it under the terms of the GNU General Public License as published by
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jpayne@69
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10 * the Free Software Foundation; either version 2 of the License, or
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jpayne@69
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11 * (at your option) any later version.
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jpayne@69
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12 *
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13 * This program is distributed in the hope that it will be useful,
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jpayne@69
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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jpayne@69
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16 * GNU General Public License for more details.
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jpayne@69
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17 *
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18 * You should have received a copy of the GNU General Public License
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jpayne@69
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19 * along with this program; if not, write to the Free Software
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jpayne@69
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20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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jpayne@69
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21 *
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22 */
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jpayne@69
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23 #ifndef __SOUND_EMU10K1_H
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jpayne@69
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24 #define __SOUND_EMU10K1_H
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25
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jpayne@69
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26 #ifdef __linux__
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jpayne@69
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27 #include <linux/types.h>
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28 #endif
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29
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jpayne@69
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30 /*
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jpayne@69
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31 * ---- FX8010 ----
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32 */
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33
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jpayne@69
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34 #define EMU10K1_CARD_CREATIVE 0x00000000
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jpayne@69
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35 #define EMU10K1_CARD_EMUAPS 0x00000001
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36
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jpayne@69
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37 #define EMU10K1_FX8010_PCM_COUNT 8
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38
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jpayne@69
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39 /*
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40 * Following definition is copied from linux/types.h to support compiling
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41 * this header file in userspace since they are not generally available for
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jpayne@69
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42 * uapi headers.
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43 */
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jpayne@69
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44 #define __EMU10K1_DECLARE_BITMAP(name,bits) \
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45 unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
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46
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jpayne@69
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47 /* instruction set */
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jpayne@69
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48 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
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jpayne@69
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49 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
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jpayne@69
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50 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
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jpayne@69
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51 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
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jpayne@69
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52 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
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jpayne@69
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53 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
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jpayne@69
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54 #define iACC3 0x06 /* R = A + X + Y ; saturation */
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jpayne@69
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55 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
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jpayne@69
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56 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
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jpayne@69
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57 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
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jpayne@69
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58 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
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jpayne@69
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59 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
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jpayne@69
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60 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
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jpayne@69
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61 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
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jpayne@69
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62 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
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jpayne@69
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63 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
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64
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jpayne@69
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65 /* GPRs */
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jpayne@69
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66 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
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jpayne@69
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67 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
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jpayne@69
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68 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
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jpayne@69
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69 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
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jpayne@69
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70 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
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71
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72 #define C_00000000 0x40
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73 #define C_00000001 0x41
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74 #define C_00000002 0x42
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jpayne@69
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75 #define C_00000003 0x43
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jpayne@69
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76 #define C_00000004 0x44
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jpayne@69
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77 #define C_00000008 0x45
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jpayne@69
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78 #define C_00000010 0x46
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jpayne@69
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79 #define C_00000020 0x47
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80 #define C_00000100 0x48
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jpayne@69
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81 #define C_00010000 0x49
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jpayne@69
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82 #define C_00080000 0x4a
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83 #define C_10000000 0x4b
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jpayne@69
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84 #define C_20000000 0x4c
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jpayne@69
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85 #define C_40000000 0x4d
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jpayne@69
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86 #define C_80000000 0x4e
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jpayne@69
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87 #define C_7fffffff 0x4f
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jpayne@69
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88 #define C_ffffffff 0x50
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jpayne@69
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89 #define C_fffffffe 0x51
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jpayne@69
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90 #define C_c0000000 0x52
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jpayne@69
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91 #define C_4f1bbcdc 0x53
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jpayne@69
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92 #define C_5a7ef9db 0x54
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93 #define C_00100000 0x55 /* ?? */
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jpayne@69
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94 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
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jpayne@69
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95 #define GPR_COND 0x57 /* CCR, condition register */
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jpayne@69
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96 #define GPR_NOISE0 0x58 /* noise source */
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jpayne@69
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97 #define GPR_NOISE1 0x59 /* noise source */
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jpayne@69
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98 #define GPR_IRQ 0x5a /* IRQ register */
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jpayne@69
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99 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
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jpayne@69
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100 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
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jpayne@69
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101 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
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jpayne@69
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102 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
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jpayne@69
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103 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
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jpayne@69
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104 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
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105
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106 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
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jpayne@69
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107 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
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jpayne@69
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108 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
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109 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
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110 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
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111 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
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112
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113 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
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114 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
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115 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
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116 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
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117 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
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118 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
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119 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
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120 #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
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121 #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
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122 #define A_GPR(x) (A_FXGPREGBASE + (x))
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123
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124 /* cc_reg constants */
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125 #define CC_REG_NORMALIZED C_00000001
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126 #define CC_REG_BORROW C_00000002
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127 #define CC_REG_MINUS C_00000004
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128 #define CC_REG_ZERO C_00000008
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129 #define CC_REG_SATURATE C_00000010
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130 #define CC_REG_NONZERO C_00000100
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131
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132 /* FX buses */
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133 #define FXBUS_PCM_LEFT 0x00
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134 #define FXBUS_PCM_RIGHT 0x01
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135 #define FXBUS_PCM_LEFT_REAR 0x02
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136 #define FXBUS_PCM_RIGHT_REAR 0x03
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jpayne@69
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137 #define FXBUS_MIDI_LEFT 0x04
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138 #define FXBUS_MIDI_RIGHT 0x05
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139 #define FXBUS_PCM_CENTER 0x06
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140 #define FXBUS_PCM_LFE 0x07
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141 #define FXBUS_PCM_LEFT_FRONT 0x08
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142 #define FXBUS_PCM_RIGHT_FRONT 0x09
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143 #define FXBUS_MIDI_REVERB 0x0c
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144 #define FXBUS_MIDI_CHORUS 0x0d
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145 #define FXBUS_PCM_LEFT_SIDE 0x0e
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146 #define FXBUS_PCM_RIGHT_SIDE 0x0f
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147 #define FXBUS_PT_LEFT 0x14
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148 #define FXBUS_PT_RIGHT 0x15
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149
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jpayne@69
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150 /* Inputs */
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jpayne@69
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151 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
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jpayne@69
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152 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
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jpayne@69
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153 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
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154 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
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155 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
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jpayne@69
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156 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
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jpayne@69
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157 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
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jpayne@69
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158 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
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jpayne@69
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159 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
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jpayne@69
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160 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
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jpayne@69
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161 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
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jpayne@69
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162 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
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jpayne@69
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163 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
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jpayne@69
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164 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
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165
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166 /* Outputs */
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jpayne@69
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167 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
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jpayne@69
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168 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
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jpayne@69
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169 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
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170 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
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jpayne@69
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171 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
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jpayne@69
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172 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
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173 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
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174 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
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175 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
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jpayne@69
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176 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
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jpayne@69
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177 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
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jpayne@69
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178 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
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jpayne@69
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179 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
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180 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
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181 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
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jpayne@69
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182 #define EXTOUT_ACENTER 0x11 /* Analog Center */
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jpayne@69
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183 #define EXTOUT_ALFE 0x12 /* Analog LFE */
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184
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jpayne@69
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185 /* Audigy Inputs */
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jpayne@69
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186 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
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jpayne@69
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187 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
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jpayne@69
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188 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
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jpayne@69
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189 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
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jpayne@69
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190 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
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jpayne@69
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191 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
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jpayne@69
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192 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
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jpayne@69
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193 #define A_EXTIN_LINE2_R 0x09 /* right */
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jpayne@69
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194 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
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jpayne@69
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195 #define A_EXTIN_ADC_R 0x0b /* right */
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196 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
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197 #define A_EXTIN_AUX2_R 0x0d /* - right */
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198
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jpayne@69
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199 /* Audigiy Outputs */
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jpayne@69
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200 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
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jpayne@69
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201 #define A_EXTOUT_FRONT_R 0x01 /* right */
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jpayne@69
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202 #define A_EXTOUT_CENTER 0x02 /* digital front center */
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jpayne@69
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203 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
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jpayne@69
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204 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
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jpayne@69
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205 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
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jpayne@69
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206 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
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jpayne@69
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207 #define A_EXTOUT_REAR_R 0x07 /* right */
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jpayne@69
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208 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
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jpayne@69
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209 #define A_EXTOUT_AFRONT_R 0x09 /* right */
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jpayne@69
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210 #define A_EXTOUT_ACENTER 0x0a /* analog center */
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jpayne@69
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211 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
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jpayne@69
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212 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
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213 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
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214 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
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jpayne@69
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215 #define A_EXTOUT_AREAR_R 0x0f /* right */
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jpayne@69
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216 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
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jpayne@69
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217 #define A_EXTOUT_AC97_R 0x11 /* right */
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jpayne@69
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218 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
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jpayne@69
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219 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
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jpayne@69
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220 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
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221
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jpayne@69
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222 /* Audigy constants */
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jpayne@69
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223 #define A_C_00000000 0xc0
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224 #define A_C_00000001 0xc1
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jpayne@69
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225 #define A_C_00000002 0xc2
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jpayne@69
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226 #define A_C_00000003 0xc3
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227 #define A_C_00000004 0xc4
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jpayne@69
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228 #define A_C_00000008 0xc5
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229 #define A_C_00000010 0xc6
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230 #define A_C_00000020 0xc7
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jpayne@69
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231 #define A_C_00000100 0xc8
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232 #define A_C_00010000 0xc9
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jpayne@69
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233 #define A_C_00000800 0xca
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jpayne@69
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234 #define A_C_10000000 0xcb
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235 #define A_C_20000000 0xcc
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236 #define A_C_40000000 0xcd
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237 #define A_C_80000000 0xce
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238 #define A_C_7fffffff 0xcf
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jpayne@69
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239 #define A_C_ffffffff 0xd0
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240 #define A_C_fffffffe 0xd1
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jpayne@69
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241 #define A_C_c0000000 0xd2
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jpayne@69
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242 #define A_C_4f1bbcdc 0xd3
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jpayne@69
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243 #define A_C_5a7ef9db 0xd4
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jpayne@69
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244 #define A_C_00100000 0xd5
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jpayne@69
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245 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
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jpayne@69
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246 #define A_GPR_COND 0xd7 /* CCR, condition register */
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jpayne@69
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247 #define A_GPR_NOISE0 0xd8 /* noise source */
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jpayne@69
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248 #define A_GPR_NOISE1 0xd9 /* noise source */
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jpayne@69
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249 #define A_GPR_IRQ 0xda /* IRQ register */
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250 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
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jpayne@69
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251 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
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252
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jpayne@69
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253 /* definitions for debug register */
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254 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
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255 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
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256 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
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jpayne@69
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257 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
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jpayne@69
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258 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
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jpayne@69
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259 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
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260 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
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261
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jpayne@69
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262 /* tank memory address line */
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jpayne@69
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263 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
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jpayne@69
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264 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
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jpayne@69
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265 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
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jpayne@69
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266 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
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jpayne@69
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267 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
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268
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269 struct snd_emu10k1_fx8010_info {
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270 unsigned int internal_tram_size; /* in samples */
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271 unsigned int external_tram_size; /* in samples */
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272 char fxbus_names[16][32]; /* names of FXBUSes */
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273 char extin_names[16][32]; /* names of external inputs */
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274 char extout_names[32][32]; /* names of external outputs */
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jpayne@69
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275 unsigned int gpr_controls; /* count of GPR controls */
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276 };
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277
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278 #define EMU10K1_GPR_TRANSLATION_NONE 0
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279 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
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280 #define EMU10K1_GPR_TRANSLATION_BASS 2
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jpayne@69
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281 #define EMU10K1_GPR_TRANSLATION_TREBLE 3
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282 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
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283
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284 enum emu10k1_ctl_elem_iface {
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285 EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */
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286 EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */
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287 };
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288
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jpayne@69
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289 struct emu10k1_ctl_elem_id {
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290 unsigned int pad; /* don't use */
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291 int iface; /* interface identifier */
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jpayne@69
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292 unsigned int device; /* device/client number */
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jpayne@69
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293 unsigned int subdevice; /* subdevice (substream) number */
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jpayne@69
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294 unsigned char name[44]; /* ASCII name of item */
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jpayne@69
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295 unsigned int index; /* index of item */
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jpayne@69
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296 };
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297
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jpayne@69
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298 struct snd_emu10k1_fx8010_control_gpr {
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299 struct emu10k1_ctl_elem_id id; /* full control ID definition */
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jpayne@69
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300 unsigned int vcount; /* visible count */
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jpayne@69
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301 unsigned int count; /* count of GPR (1..16) */
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jpayne@69
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302 unsigned short gpr[32]; /* GPR number(s) */
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jpayne@69
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303 unsigned int value[32]; /* initial values */
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jpayne@69
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304 unsigned int min; /* minimum range */
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jpayne@69
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305 unsigned int max; /* maximum range */
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jpayne@69
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306 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
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307 const unsigned int *tlv;
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308 };
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309
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jpayne@69
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310 /* old ABI without TLV support */
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311 struct snd_emu10k1_fx8010_control_old_gpr {
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jpayne@69
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312 struct emu10k1_ctl_elem_id id;
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jpayne@69
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313 unsigned int vcount;
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jpayne@69
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314 unsigned int count;
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jpayne@69
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315 unsigned short gpr[32];
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jpayne@69
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316 unsigned int value[32];
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jpayne@69
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317 unsigned int min;
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jpayne@69
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318 unsigned int max;
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jpayne@69
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319 unsigned int translation;
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jpayne@69
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320 };
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321
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jpayne@69
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322 struct snd_emu10k1_fx8010_code {
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323 char name[128];
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324
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325 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
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326 __u32 *gpr_map; /* initializers */
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327
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jpayne@69
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328 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
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329 struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */
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330
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jpayne@69
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331 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
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jpayne@69
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332 struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */
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333
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jpayne@69
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334 unsigned int gpr_list_control_count; /* count of GPR controls to list */
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jpayne@69
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335 unsigned int gpr_list_control_total; /* total count of GPR controls */
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jpayne@69
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336 struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */
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337
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338 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
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jpayne@69
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339 __u32 *tram_data_map; /* data initializers */
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jpayne@69
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340 __u32 *tram_addr_map; /* map initializers */
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341
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342 __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
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jpayne@69
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343 __u32 *code; /* one instruction - 64 bits */
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344 };
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345
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jpayne@69
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346 struct snd_emu10k1_fx8010_tram {
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347 unsigned int address; /* 31.bit == 1 -> external TRAM */
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jpayne@69
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348 unsigned int size; /* size in samples (4 bytes) */
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jpayne@69
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349 unsigned int *samples; /* pointer to samples (20-bit) */
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jpayne@69
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350 /* NULL->clear memory */
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351 };
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352
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353 struct snd_emu10k1_fx8010_pcm_rec {
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jpayne@69
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354 unsigned int substream; /* substream number */
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jpayne@69
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355 unsigned int res1; /* reserved */
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jpayne@69
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356 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
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jpayne@69
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357 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
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jpayne@69
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358 unsigned int buffer_size; /* count of buffered samples */
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jpayne@69
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359 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
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jpayne@69
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360 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
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jpayne@69
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361 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
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jpayne@69
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362 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
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jpayne@69
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363 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
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jpayne@69
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364 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
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jpayne@69
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365 unsigned char pad; /* reserved */
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jpayne@69
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366 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
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jpayne@69
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367 unsigned int res2; /* reserved */
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368 };
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369
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370 #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
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371
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372 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
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373 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
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374 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
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375 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
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376 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
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377 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
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378 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
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379 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
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jpayne@69
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380 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
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jpayne@69
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381 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
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jpayne@69
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382 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
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jpayne@69
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383 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
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jpayne@69
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384 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
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jpayne@69
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385 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
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386
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387 #endif /* __SOUND_EMU10K1_H */
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